A programmable logic device (abbreviated hereafter to PLD) has an integrated circuit in which a plurality of logic circuit elements, memory circuit elements, wires, switches, and so on are formed in advance, and reconfigures the circuit capable of executing a predetermined process, when configuration data for configuring a circuit capable of executing the predetermined process are set in or written to the integrated circuit. This type of PLD is a field programmable gate array (FPGA) or the like, for example, and serves as an LSI in which an internal circuit can be reconfigured to various logic circuits by rewriting configuration data. Hereafter, an FPGA will be described as an example of a PLD.
When a processor causes a dedicated hardware circuit to execute a predetermined software process (a job, for example), a processor set or writes configuration data for configuring the dedicated circuit in an FPGA to configure the dedicated circuit in the FPGA, and then causes the dedicated circuit to execute the predetermined process. Further, when the dedicated circuit completes the predetermined process, the processor set or writes configuration data of another dedicated circuit in the FPGA that executes another process to configure the other dedicated circuit in the FPGA, and then causes the other dedicated circuit to execute the other process. The processor causes a dedicated circuit of the FPGA to execute a predetermined software process, whereby the FPGA acts as an accelerator of the processor. As a result, power saving and improved functionality can be realized in an information processing device (a computer) that includes the processor.
With increases in the scale of FPGAs, it has become possible to configure a plurality of logic circuits in an FPGA and operate the plurality of logic circuits in parallel. It has also become possible to reconfigure the plurality of logic circuits configured in the FPGA dynamically and asynchronously such that the plurality of logic circuits are operated asynchronously in parallel, for example by reconfiguring a part of the plurality of logic circuits and starting to operate the resulting new logic circuits while continuing to operate the plurality of logic circuits.
Configuring a plurality of circuits in an FPGA is disclosed in Japanese Laid-open Patent Publication No. 2016-76867 and Japanese Laid-open Patent Publication No. 2015-231205.